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ADP3121
12 V
4
V CC
D1
ADP3121
1
BST
C BST2
IN 2
LATCH
R1
R2 Q
S
8
C BST1
DRVH
R G
Q1
DELAY
7
SW
R BST
TO
INDUCTOR
CMP
CMP
V CC
6
OD 3
1V
DELAY
CONTROL
LOGIC
5
6
DRVL
PGND
Q2
Figure 1. Block Diagram
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
Pin Name
BST
IN
OD
VCC
DRVL
PGND
SW
DRVH
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds
this bootstrapped voltage for the high ? side MOSFET while it is switching.
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this
pin low turns on the low ? side driver; pulling it high turns on the high ? side driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with an ~1 m F ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched
voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
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